SC402B
26
Applications Information (continued)
virtual ESR network that is composed of two capacitors
and one resistor, as shown in Figure 13.
R
1
R
2
FB
pin
C
C
C
OUT
L
C
L
R
L
DCR
D x V
IN
+
-
V
L
Figure 13 Virtual ESR Ramp Circuit
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across C
L
and output ripple voltage.
They are defined in the following equations.
1
C
R
S
)
1
DCR
/
L
s
(
DCR
I
Vc
L
L
L
L
SW
L
OUT
f
C
8
I
V
Figure 14 shows the magnitude of the ripple contribution
due to C
L
at the FB pin.
R
1
R
2
FB
pin
C
C
L
C
L
R
L
DCR
D x V
IN
+
-
V
L
Figure 14 FB Voltage by CL Voltage
It is shown by the following equation.
1
C
S
R
//
R
C
S
R
//
R
Vc
VFBc
C
2
1
C
2
1
L
L
Figure 15 shows the magnitude of the ripple contribution
due to the output voltage ripple at the FB pin.
R
1
R
2
FB
pin
C
C
C
OUT
L
C
L
R
L
DCR
V
L
V
OUT
R
1
R
2
V
OUT
C
C
FB
pin
C
OUT
Figure 15 FB Voltage by Output Voltage
It is shown by the following equation.
2
C
1
2
OUT
OUT
R
C
S
1
//
R
R
V
V
VFB
The purpose of this network is to couple the inductor
current ripple information into the feedback voltage such
that the feedback voltage has 90 degrees phase lag to the
switching node similar to the case of using standard high
ESR capacitors. This is illustrated in Figure 16.
V
OUT
LX
I
L
FB contribution
by C
L
FB contribution by
output voltage ripple
Combined FB
Figure 16 FB voltage in Phasor Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from C
L
, is controlled by
the value of R
1
, R
2
and C
C
. If the corner frequency of (R
1
//
R
2
) x C
C
is too high, the ripple magnitude at the FB pin will
be smaller, which can lead to double-pulsing. Conversely,
if the corner frequency of (R
1
// R
2
) x C
C
is too low, the
ripple magnitude at FB pin will be higher. Since the
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